Thinned, back illuminated, semiconductor imaging devices are advantageous over front-illuminated imagers for high fill factor and better overall efficiency of charge carrier generation and collection. A desired property of such devices is that the charge carriers generated by light or other emanation incident on the back side should be driven to the front side quickly to avoid any horizontal drift, which may smear the image. It is also desirable to minimize the recombination of the generated carriers before they reach the front side, since such recombination reduces overall efficiency and sensitivity of the device.
This desired property may be achieved by providing a thin semiconductor layer and a high electric field within this layer. The field should extend to the back surface, so that the generated carriers, such as electrons or holes, can be driven quickly to the front side. This requires additional treatment at the backside of the device, which adds to complexity of the fabrication process. One current technique includes chemical thinning of semiconductor wafers and deposition of a “flash gate” at the backside after thinning. This requires critical thickness control of the backside flash gate. Another technique involves growth of a thin dopant layer on a wafer back using molecular beam epitaxy (MBE). Still another known method used to provide a desired electric field is to create a gradient of doping inside the thinned semiconductor layer by backside implant of the layer followed by appropriate heat treatment for annealing and activation.
These methods can not be easily included in conventional semiconductor foundry processing, and require more expensive custom processing. They are therefore often not cost-effective and not suitable for commercial manufacturing.
Electron-hole pairs generated near the back surface of a back-illuminated imager need to be driven away from the back surface due to another feature of the manufacturing process. One process step employed during the fabrication of back illuminated imagers is back thinning of the silicon substrate. This may involve partial or total removal of the substrate to expose a thinned back surface. The thinning process introduces electrical trap sites on the back surface of the imager. Due to inherent dangling bonds present at or near the back surface of the imager, optically generated electrons inside the substrate will tend to recombine at the back surface. Therefore, Quantum Efficiency (QE) may be degraded if generated electrons are allowed to reach the back surface. To prevent the charge carriers from moving towards the back surface, the back surface needs to be treated in such a way that the back surface is electrically pinned, i.e., the back surface should be saturated with a high enough concentration of electrons such that generated electrons moving toward the back surface are repelled toward the front surface of the imager.
An electrically pinned back surface may provide an appropriate electric field because of band bending, and thus prevent the recombination of photo generated charge carriers at the back surface. Backside pinning is typically achieved by ion implantation of an appropriate impurity type and high temperature ion activation by furnace annealing. High temperature furnace annealing results in a uniform and stable doping profile near the back surface. FIG. 1 shows a typical backside boron profile of a thinned p-type substrate which is electrically pinned. The boron concentration gradient at the back surface as shown in FIG. 1 provides the necessary electric field to block optically generated electrons from moving towards the back surface. However, the high temperature ion activation furnace annealing imposes several restrictions on the process sequence, such as metal deposition. Other techniques such as laser annealing and flash oxide deposition are currently being pursued. These techniques, however, are considered to be undesirable for producing low cost, highly manufacturable back-illuminated imagers. In addition, the thinning process poses yield issues such as stress in the thinned wafer, and non-uniformity of thickness. Fabrication costs for current fabricating techniques for producing thinned back-illuminated imagers with back side pinning is high compared to non-pinned fabrication methods.
A technique for producing highly manufacturable, low cost back illuminated imagers that exhibits an internal electric field that drives electrons toward the front side of the imager is disclosed in U.S. Pat. No. 7,238,583 by Swain et. al. (the “'583 patent”), which is incorporated herein by reference in its entirety. In addition to the desired internal electric field, the device of the '583 patent also employs ultra thin Silicon-on-Insulator (UTSOI) technology for providing a semiconductor substrate on which the back-illuminated imager is constructed.
To manufacture the UTSOI imager of the '583 patent, the starting structure is an initial substrate, sometimes referred to in the art as a UTSOI substrate. The starting UTSOI substrate is composed of a mechanical substrate (handle wafer) configured to provide mechanical support during processing, an insulator layer 14 (which can be, for example, a buried oxide layer of silicon (BOX)), and a semiconductor substrate (also referred to as the “seed layer”). The seed layer is doped with a high concentration of p or n-type dopant, typically boron. An epitaxial layer is grown overlying the doped seed layer. The epitaxial layer provides a layer for fabricating front side components which complete the overall imaging device. During the growth of epitaxial layer, dopants previously introduced into the seed layer diffuse into the epitaxial layer. At the conclusion of the growth of the epitaxial layer, a net final doping profile is created. Once the epitaxial layer is grown, one or more imaging components may be fabricated in the epitaxial layer using known methods of semiconductor fabrication.
Processing parameters such as doping levels, initial doping profiles, and temperatures are chosen to give the desired doping profile, as shown in FIG. 2, reproduced from the '583 patent show the results of computer simulations of a desired net doping profile. In FIG. 2, Region 130 corresponds to the insulator layer; Region 120 corresponds to the seed layer; Region 100 corresponds to the epitaxial layer; reference number 125 corresponds to the interface between the seed layer and the insulator layer; and reference number 110 corresponds to an interface between the seed layer and the epitaxial layer.
FIG. 2 shows a net final doping profile 140 after growth of the epitaxial layer 100. The net final doping profile 140 in this simulated process exhibits the following desirable features: it has a maximum value at the interface 125 between the seed layer 120 and the insulator layer 130 and decreases monotonically with increasing distance from the interface 125 within the seed layer 120 and the epitaxial layer 100. The UTSOI back-illuminated imager of the '583 patent thus has a back side at the interface 125 between the seed layer 120 and the insulator layer 130 that is electrically pinned by means of the introduction of a monotonically decreasing net doping concentration within the seed layer 120 and the epitaxial layer 100.
Accordingly, what would be desirable, but has not yet been provided, is a method and resulting device for producing thinned CCD/CMOS back illuminated imagers based on UTSOI technology which has a pinned back surface and an internal electric field which drives electrons toward the front surface, but does not require the introduction of impurities to produce a monotonically decreasing net doping profile.